"will two atomic writes to different locations in different threads always be seen in the same order by other threads?" Code Answer

the updated¹ code in the question (with loads of x and y swapped in thread 4) does actually test that all threads agree on a global store order.

under the c++11 memory model, the outcome r1==1, r2==0, r3==2, r4==0 is allowed and in fact observable on power.

on x86 this outcome is not possible, because there "stores are seen in a consistent order by other processors". this outcome is also not allowed in a sequential consistent execution.

footnote 1: the question originally had both readers read x then y. a sequentially consistent execution of that is:

-- initially --
std::atomic<int> x{0};
std::atomic<int> y{0};

-- thread 4 --
int r3 = x.load(std::memory_order_acquire);

-- thread 1 --
x.store(1, std::memory_order_release);

-- thread 3 --
int r1 = x.load(std::memory_order_acquire);
int r2 = y.load(std::memory_order_acquire);

-- thread 2 --
y.store(2, std::memory_order_release);

-- thread 4 --
int r4 = y.load(std::memory_order_acquire);

this results in r1==1, r2==0, r3==0, r4==2. hence, this is not a weird outcome at all.

to be able to say that each reader saw a different store order, we need them to read in opposite orders to rule out the last store simply being delayed.

By Karen White on January 26 2022